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Title: LowLAG: Low-latency hardware accelerator of a sound effect with system-on-chip design
Authors: Esen, Y.E.
Şan, İsmail
Keywords: hardware accelerator
sound effect
system-onchip design
Issue Date: 2020
Publisher: Institute of Electrical and Electronics Engineers Inc.
Abstract: Many sound effects such as Autotune are very popular among artists to be used in live concerts. However, latency problems may occur when using these effects. This latency may affect the artists negatively. Latency of audio processing in CPU-based systems is a significant issue and does not provide minimal worst-case latency values for many high-end musical devices to be used in live concerts. This paper investigates how to achieve a low-latency audio processing with hardware and software co-design methodology in FPGA-based systems by designing an application-specific system-on-chip (SoC) architecture containing a hardware accelerator to generate a sound effect. The accelerator is connected to an ARM processor core within a Zynq-based programmable SoC platform. The ARM processor core is responsible (1) to handle data movement operations, (2) to enable or disable the sound effect over captured audio signal and (3) to perform some of the operations of the sound effect algorithm. The sound effect algorithm is designed in MATLAB Simulink and corresponding hardware is generated through the HDL Coder. Our main objective is to reduce the audio latency of sound effect processing from input to output by designing a sound effect-specific hardware IP core via MATLAB Simulink and incorporating it on a custom SoC architecture. SoC solution is prototyped in ZedBoard that contains ZC7020 Zynq chip and this low-end embedded SoC system outperforms the CPU-based solution. © 2020 IEEE.
Description: 2020 Innovations in Intelligent Systems and Applications Conference, ASYU 2020 -- 15 October 2020 through 17 October 2020 -- -- 165305
ISBN: 9.78E+12
Appears in Collections:Scopus İndeksli Yayınlar Koleksiyonu

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