Please use this identifier to cite or link to this item: https://hdl.handle.net/20.500.13087/702
Title: A LOW AREA FULLY PIPELINED IMPLEMENTATION OF JPEG ON FPGA
Authors: Doğan, Atakan
Şan, İsmail
Issue Date: 2018
Abstract: This paper presents a low-area and high-throughput design and implementation of JPEG encoder on FPGA. The design consists of three main components: (1) 2-D DCT module, employing the row-column decomposition technique, (2) Quantization in zigzag ordering, utilizing look-up tables, and (3) Entropy coder, transforming the quantized DCT coefficients into JPEG words. All components are fully pipelined and optimized for FPGA resource utilization. The proposed implementation of JPEG encoder is able to encode 143 and 71 SDTV frames per second with 720x480 gray scale and color pixels per frame, respectively, on Xilinx Spartan 6 FPGA. Moreover, the proposed architecture is capable of encoding at least 53 and 26 HD Ready TV frames per second with 1280x720 gray scale and color pixels per frame, respectively, on this FPGA chip. Thus, the proposed JPEG encoder architecture is well-suited to various image and video compressing applications where performance and area are significantly important.
URI: https://doi.org/10.18038/aubtda.422250
https://hdl.handle.net/20.500.13087/702
https://search.trdizin.gov.tr/yayin/detay/359165
ISSN: 1302-3160
2667-4211
Appears in Collections:Kimya Bölümü Koleksiyonu
TR-Dizin İndeksli Yayınlar Koleksiyonu

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