Please use this identifier to cite or link to this item: https://hdl.handle.net/20.500.13087/150
Title: On the Importance of Improving Cache Locality in Application-specific Accelerators via HLS
Authors: Alptekin, Yasin
Şan, İsmail
Keywords: Locality
cache
domain-specific accelerator
system-on-chip
FPGA
Issue Date: 2020
Publisher: IEEE
Abstract: Designing an hardware architecture using a low-level hardware description language (Verilog, VHDL) is a difficult and time-consuming task especially when the application is a complex and memory intensive one A high-level synthesis (ELS) tool, most recently and actively being researched in several research groups, automatically generates an RTL description of the hardware architecture from a high-level (C/C++) program. However, application to be accelerated on the hardware via an HLS tool needs to be written in order to decrease the overall memory access latency by simply rewriting the code so that the reformatted loop structure will have more locality. In this paper, we present two case studies to decrease the memory access latency by improving the locality of a given application by reorganizing the memory access pattern of the application being accelerated via HLS on hardware that has a cache. We also emphasize the importance of locality in performance of hardware accelerators with our empirical results on a Zynq-based SoC platform.
Description: 28th Signal Processing and Communications Applications Conference (SIU) -- OCT 05-07, 2020 -- ELECTR NETWORK
URI: https://hdl.handle.net/20.500.13087/150
ISBN: 978-1-7281-7206-4
ISSN: 2165-0608
Appears in Collections:Elektrik-Elektronik Mühendisliği Bölümü Koleksiyonu
WoS İndeksli Yayınlar Koleksiyonu

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